1. Field of the Invention
The present invention relates to programmable logic arrays (PLAs). More specifically, the present invention relates to voltage pumps used in programmable array logic (PAL) circuits.
While the present invention is described herein with reference to illustrative embodiments for particular applications, it should be understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional modifications, applications, and embodiments within the scope thereof and additional fields in which the present invention would be of significant utility.
2. Description of the Related Art
Programmable logic arrays provide `glue logic` for PC (printed circuit) boards. Glue logic is the logic required to interface two boards and generally includes a plurality of AND gates, OR gates and input/output I/O buffers. PLAs consume less space and therefore generally provide glue logic in a less costly manner than individual AND gates, OR gates and I/O buffers.
PLAs also offer the advantage of reconfigurability over discrete or individual gates. That is, PLAs generally include an array of `AND` gates, an array of `OR` gates, and some provision for interconnecting the outputs of selected AND gates to the inputs of selected OR gates. PLAs allow a wide variety of logic functions to be implemented through the combination, via the OR gates, of the product terms, provided by the AND gates. Further, the configuration of the array may be quickly, easily and relatively inexpensively reprogrammed to implement other functions.
As described in U.S. Pat. No. 4,124,899, programmable array logic (PAL) circuits were developed to provide further improvements in the speed, space requirements, cost and power consumption of PLAs. PALs provide programmable AND and fixed OR functions. In a most general sense, a PAL provides a field programmable logic array in which a programmable array of circuit inputs are provided to a plurality of AND gates (cells) to generate product terms. Outputs from subgroups of AND gates are, in turn, nonprogrammably connected as inputs to individual, specified OR gates to provide the sum of products.
The programming circuit of the electrically erasable PAL type logic array typically includes an input term decoder circuit, a product term decoder circuit, a margin control circuit and a sense line control circuit. These decoders and control circuits require a number of voltage levels at different times during the programming of the EE array. A high voltage may be required for programming certain circuits while the other circuits may require low, zero, or other (floating state) voltages. Where high voltages are required, the voltages required may exceed the externally supplied voltage.
In conventional PAL devices, the programming circuits typically include individual high voltage charge pumps to provide the high voltages needed for the programming operation. Each charge pump typically includes a capacitive oscillator in the source circuit of a n-channel metal-oxide (NMOS) transistor. The capacitor is fed with a clock pulse which incrementally increases the voltage at the output of the device above the externally supplied voltage. Each voltage pump requires a connection to the external voltage source, a connection to the system clock, and connections for one or more programming control signals. As one such charge pump is typically provided for each of numerous programming circuits, it is clear that considerable die area is consumed by the multiplicity of charge pump circuits and lines associated therewith in conventional PAL devices.
Thus, there is a need in the art for a simple, effective high voltage pumping scheme for PAL type programmable logic arrays which requires few interconnections and minimum die area.